DfT Senior Architect
NXP
Nijmegen
3 dagen geleden

NXP Semiconductors N.V. enables secure connections for a smarter world, advancing solutions that make lives easier, better, and safer.

As the world leader in secure connectivity solutions for embedded applications, NXP is driving innovation in the automotive, industrial & IoT, mobile, and communication infrastructure markets.

Built on more than 60 years of combined experience and expertise, the company has approximately 30,000 employees in more than 30 countries and posted revenue of $9.41 billion in 2018.

The DfT-Architect coordinates across IC architecture, DfT, Design and Test & Product engineering disciplines. He / she is responsible for the DfT Architecture and proper implementation in the design.

Overall goal is to aim for an optimal industrial test concept and an appropriate DfT realization according to the required test cost vs.

product quality balance within the project determined constraints. His / her focus is on complex RF (radar / radio) SOC projects.

The DfT-Architect is the technical lead of the DfT-implementation team and advises analog and digital IP designers and software engineers.

Primary Accountabilities :

  • Responsible for the testability requirements of the IC / IP and its composing modules.
  • Defines test strategy and DfT architecture to achieve the specified quality level for lowest integral test cost.
  • Advises and defines the system / hardware architect on testability provisions in the IC / IP architecture to enable high test-coverage and easy test access.
  • Specifies chip level test concepts requirements
  • Supports predictions on factory yields, fall-off rate, delivery quality, test coverage, test cycle time and test costs.
  • Guides the DfT-implementation team and validation team and assists appropriate digital and analog designers.
  • Supports and consults design team members on test related issues, as well as coaches test- and product engineers in the area of Design-for-Testability.
  • Aids the test engineering during test program development and debug
  • Candidate profile :

  • 10+ years experience in Semiconductor
  • M.Sc. degree in Electronic Engineering or similar
  • Experience with logic design (System Verilog and VHDL), ASIC design flow, clocking and reset methods, experience with EDA tools
  • Experience with analog design ánd familiar with Design-for-Test including mixed signal DfT methods
  • Good understanding of fault models, ATPG, scan insertion and compression techniques, BIST and JTAG
  • Open proactive communicator, enjoys interactive and iterative development process
  • Structured manager
  • What’s next

    If you are as excited about this opportunity as we are, we kindly invite you to apply. After a screening based on your profile, you can be expected to have a phone interview with our Talent Acquisition Consultant followed by several business interviews.

    deze vacature melden
    checkmark

    Thank you for reporting this job!

    Your feedback will help us improve the quality of our services.

    Solliciteren
    Mijn E-mail
    Door op "Doorgaan" te klikken, betekent dit dat je neuvoo toestemming geeft om je gegevens te verwerken en je e-mails met vacatures te sturen, zoals beschreven in neuvoo's -Privacybeleid . Je kunt je toestemming altijd intrekken
    Doorgaan
    Aanvraagformulier